参数资料
型号: MIC3001BML TR
厂商: Micrel Inc
文件页数: 59/76页
文件大小: 0K
描述: IC FOM MANAGEMENT W/CALIBR 24MLF
标准包装: 1,000
类型: 收发器
规程: SDHj Sonet
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘,24-MLF?
供应商设备封装: 24-MLF?(4x4)
包装: 带卷 (TR)
其它名称: MIC3001BMLTR
MIC3001BMLTR-ND
Micrel, Inc.
MIC3001
August 2004
62
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Byte
Weight
3
OEM Password, Most Significant Byte
2
OEM Password, 2nd Most Significant Byte
1
OEM Password, 2nd Least Significant Byte
0
OEM Password, Least Significant Byte
OEM Calibration 0 (OEMCAL0)
D[7]
reserved
D[6]
FLTDIS
read/write
D[5]
FSPIN
read/write
D[4]
WRINH
read/write
D[3]
APCCAL
read/write
D[2]
FRCINT
read/write
D[1]
FRCTXF
read/write
D[0]
FRCLOS
read/write
Default Value
0000 0000b = 00h
Serial Address
A6h = 1010011b
Byte Address
16 = 10h
A valid OEM password is required for access to this register.
Bit
Function
Operation
D[7]
Reserved
Always write as zero; reads undefined.
D[6]
FLTDIS
Fault comparator disable; inhibits
output of fault comparators when set.
0 = faults enabled; 1 = disabled; Read/write.
D[5]
FSPIN
Fault comparator “spin-on-channel”
mode select; do not enable ADC and
FC spin-on-channel modes
simultaneously.
0 = normal operation; 1 = spin on channel; Read/write.
D[4]
WRINH
Inhibit NVRAM write cycles.
0 = normal operation; 1 = inhibit writes; Read/write.
D[3]
APCCAL
Selects APC calibration mode - DACs
may be controlled directly.
0 = normal mode; 1 = calibration mode; Read/write.
D[2]
FRCINT
Forces the assertion of /INT
0 = normal operation; 1 = asserted; Read/write.
D[1]
FRCTXF
Forces the assertion of TXFAULT
0 = normal operation; 1 = asserted; Read/write.
D[0]
FDCLOS
Forces the assertion of RXLOS
0 = normal operation; 1 = asserted; Read/write.
OEM Calibration 1 (OEMCAL1)
D[7]
reserved
D[6]
ADSTP
read/write
D[5]
ADIDL
read/write
D[4]
1SHOT
read/write
D[3]
ADSPIN
read/write
D[2]
SPIN[2]
read/write
D[1]
SPIN[1]
read/write
D[0]
SPIN[0]
read/write
Default Value
0000 0000b = 00h
Serial Address
A6h = 1010011b
Byte Address
17 = 11h
A valid OEM password is required for access to this register.
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