参数资料
型号: ML9041-XXBCVWA
厂商: LAPIS SEMICONDUCTOR CO LTD
元件分类: 显示控制器
英文描述: 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175
封装: 10.62 X 2.55 MM, GOLD BUMP, DIE-175
文件页数: 35/61页
文件大小: 572K
代理商: ML9041-XXBCVWA
PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
39/60
Expansion Instruction Codes
The busy status of the ML9041 is rather longer than the cycle time of the CPU, since the internal processing of the
ML9041 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the
ML9041 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
“0” before sending an expansion instruction code to the ML9041.
1) Arbitrator Display Line Set
RS1
0
RS0
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
AS
Expansion instruction code:
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
CSR
duty
AS bit
Shift direction
Arbitrator’s common pin
L1/9
L
COM1
→COM9
COM9
L1/9
H
COM2
→COM9, COM1
COM1
L1/12
L
COM1
→COM12
COM12
L1/12
H
COM2
→COM12, COM1
COM1
L1/17
L
COM1
→COM17
COM17
L1/17
H
COM2
→COM17, COM1
COM1
H1/9
L
COM9
→COM1
COM1
H1/9
H
COM8
→COM1, COM9
COM9
H1/12
L
COM12
→COM1
COM1
H1/12
H
COM11
→COM1, COM12
COM12
H1/17
L
COM17
→COM1
COM1
H1/17
H
COM16
→COM1, COM17
COM17
2) Contrast Adjusting Data Write
RS1
0
RS0
0
R/W
0
DB7
0
DB6
0
DB5
1
DB4
F4
DB3
F3
DB2
F2
DB1
F1
DB0
F0
Expansion instruction code:
This instruction writes contrast adjusting data (F
4 to F0) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V
5 pin varies
according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal) and becomes
minimum when it is “00” (hexadecimal).
Note: The execution time of this instruction is 37
s at an oscillation frequency (OSC) of 270 kHz.
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