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参数资料
| 型号： | ML9041-XXBCVWA |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 显示控制器 |
| 英文描述： | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC175 |
| 封装： | 10.62 X 2.55 MM, GOLD BUMP, DIE-175 |
| 文件页数： | 59/61页 |
| 文件大小： | 572K |
| 代理商： | ML9041-XXBCVWA |
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PEDL9041-03
1Semiconductor
ML9041-xxA/xxB
6/60
Symbol
Description
T
1, T2, T3
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
V
DD
The power supply pin.
GND
The ground level input pin.
P/S
The input pin to select the parallel or serial interface.
“L” selects the parallel interface.
“H” selects the serial interface.
CS
The pin to enable this IC in the serial l/F mode.
“L” enables this IC.
“H” disables this IC.
This pin should be open in the parallel l/F mode.
SHT
The pin to input shift clock in the serial l/F mode.
Data inputting to the SI pin is carried out synchronizing with the rising edge of this
clock signal.
Data outputting from the SO pin is carried out synchronizing with the falling edge of
this clock signal.
This pin should be open in the parallel l/F mode.
Sl
The pin to input DATA in the serial l/F mode.
Data inputting to this pin is carried out synchronizing with the rising edge of the SHT
signal.
This pin should be open in the parallel l/F mode.
SO
The pin to output DATA in the serial l/F mode.
Data inputting to this pin is carried out synchronizing with the falling edge of the SHT
signal.
This pin should be open in the parallel l/F mode.
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