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| 型号： | MM908E621 |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror |
| 中文描述： | 综合四半桥和三高的嵌入式微控制器和LIN高端侧镜 |
| 文件页数： | 7/62页 |
| 文件大小： | 719K |
| 代理商： | MM908E621 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
15
908E621
Dynamic Electrical Characteristics
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN Physical Layer
Driver Characteristics for Normal Slew Rate (25), (26)
Dominant Propagation Delay TXD to LIN
tDOM-MIN
——
50
s
Dominant Propagation Delay TXD to LIN
tDOM-MAX
——
50
s
Recessive Propagation Delay TXD to LIN
tREC-MIN
——
50
s
Recessive Propagation Delay TXD to LIN
tREC-MAX
——
50
s
Duty Cycle 1: D1 = tBus_rec(min) / (2 x tBIT), tBIT = 50 s, VSUP = 7.0V..18V
D1
0.396
–
Duty Cycle 2: D2 = tBus_rec(max) / (2 x tBIT), tBIT = 50 s, VSUP = 7.6V..18V
D2
–
0.581
Dominant Propagation Delay TXD to LIN
tDOM-MIN
—
100
s
Dominant Propagation Delay TXD to LIN
tDOM-MAX
—
100
s
Recessive Propagation Delay TXD to LIN
tREC-MIN
—
100
s
Recessive Propagation Delay TXD to LIN
tREC-MAX
—
100
s
Duty Cycle 3: D3 = tBus_rec(min) / (2 x tBIT), tBIT = 96 s, VSUP = 7.0V..18V
D3
0.417
–
Duty Cycle4: D4 = tBus_rec(max) / (2 x tBIT), tBIT = 96 s, VSUP = 7.6V..18V
D4
–
0.590
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SRFAST
—20
—
V/
s
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay (28)
tRL
—3.5
6.0
s
Receiver Recessive Propagation Delay (28)
tRH
—3.5
6.0
s
Receiver Propagation Delay Symmetry
tR-SYM
-2.0
—
2.0
s
Bus Wake-Up Deglitcher
tPROPWL
30
50
150
s
Bus Wake-Up Event Reported (29)
tWAKE
—20
—
s
Notes
25.
VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k, 6.8 nF/660 , 10 nF/500 . Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
26.
27.
28.
Measured between LIN signal threshold VIL or VIH and 50% of RXD signal.
29.
tWAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 9 and Figure 8, page 19. In Sleep mode the VDD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MM908E621_08 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror |
| MM908E621ACDWB | 功能描述:8位微控制器 -MCU QUAD H-B/3-HS W/MCU & LI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MM908E621ACDWB/R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror |
| MM908E621ACDWBR2 | 功能描述:8位微控制器 -MCU QUAD HB / TRIPLE HS 841B RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MM908E621ACPEK | 功能描述:8位微控制器 -MCU QUAD H-B/3-HS W/MCU & LI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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