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| 型号： | MM908E621ACDWBR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 20/60页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HB/TRPL HISID 54-SOIC |
| 标准包装： | 1,000 |
| 应用： | 自动镜像控制 |
| 核心处理器： | HC08 |
| 程序存储器类型： | 闪存（16 kB） |
| 控制器系列： | 908E |
| RAM 容量： | 512 x 8 |
| 接口： | SCI，SPI |
| 输入/输出数： | 12 |
| 电源电压： | 9 V ~ 16 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 54-SOICW-EP |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
27
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
L0 input Interrupt
The L0 interrupt flag L0IF is set in run mode by a state
change of the L0F flag (rising or falling edge). The interrupt is
maskable with the L0IE bit in the interrupt mask register.
INTERRUPT FLAG REGISTER (IFR)
L0IF - L0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
L0 input. Clear L0IF by writing a logic [1] to L0IF. Reset clears
the L0IF bit. Writing a logic [0] to L0IF has no effect.
1 = rising or falling edge on L0 input detected
0 = no state change on L0 input detected
H0IF - H0 Input Flag Bit
This read/write flag is set on a falling or rising edge at the
H0 input. Clear H0IF by writing a logic [1] to H0IF. Reset
clears the H0IF bit. Writing a logic [0] to H0IF has no effect.
1 = state change on the hall-flags detected
0 = no state change on the hall-flags detected
LINIF - LIN Flag Bit
This read/write flag is set if a rising edge is detected and
the bus was dominant longer than TpropWL. Clear LINIF by
writing a logic [1] to LINIF. Reset clears the LINIF bit. Writing
a logic [0] to LINIF has no effect.
1 = LIN bus interrupt has occurred
0 = not LIN bus interrupt occurred since last clear
HTIF - High Temperature Flag Bit
This read/write flag is set on high temperature condition.
Clear HTIF by writing a logic [1] to HTIF. If high temperature
condition is still present while writing a logical one to HTIF,
the writing has no effect. Therefore, a high temperature
interrupt cannot be lost due to inadvertent clearing of HTIF.
Reset clears the HTIF bit. Writing a logic [0] to HTIF has no
effect.
1 = high temperature condition has occurred
0 = high temperature condition has not occurred
LVIF - Low Voltage Flag Bit
This read/write flag is set on low voltage condition. Clear
LVIF by writing a logic [1] to LVIF. If the low voltage condition
is still present while writing a logical one to LVIF, the writing
has no effect. Therefore, a low voltage interrupt cannot be
lost due to inadvertent clearing of LVIF. Reset clears the LVIF
bit. Writing a logic [0] to LVIF has no effect.
1 = low voltage condition has occurred
0 = low voltage condition has not occurred
HVIF - High Voltage Flag Bit
This read/write flag is set on a high voltage condition.
Clear HVIF by writing a logic [1] to HVIF. If the high voltage
condition is still present while writing a logical one to HVIF,
the writing has no effect. Therefore, a high voltage interrupt
cannot be lost due to inadvertent clearing of HVIF. Reset
clears the HVIF bit. Writing a logic [0] to HVIF has no effect.
1 = high voltage condition has occurred
0 = high voltage condition has not occurred
PSFIF - Power Stage Fail Bit
This read-only flag is set on a fail condition on one of the
power outputs (HBx, HSx, HVDD, H0). Reset clears the
PSFIF bit. Clear this flag by writing a logic [1] to the
appropriate fail flag.
1 = power stage fail condition has occurred
0 = power stage fail condition has not occurred
Figure 14. Principal Implementation of the PSFIF
INTERRUPT MASK REGISTER (IMR)
Register Name and Address: IFR - $0A
Bit7
6
5
4
3
2
1
Bit0
Read
L0IF
H0IF
LINIF
0
HTIF
LVIF
HVIF
PSFIF
Write
Reset
0
Register Name and Address: IMR - $09
Bit7
6
5
4
3
2
1
Bit0
Read
L0IE
H0IE
LINIE
HTRD
HTIE
LVIE
HVIE
PSFIE
Write
Reset
0
HS3OC
HS2OC
HS1OC
HB4OC
HB3OC
HB2OC
HB1OC
HVDDOCF
H0OCF
HBFF
HSFF
HVDDOCF
H0OCF
PSFIF
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