- 您现在的位置：买卖IC网 > PDF目录1954 > MM908E621ACDWBR2 (Freescale Semiconductor)IC SW QUAD HB/TRPL HISID 54-SOIC PDF资料下载
参数资料
| 型号： | MM908E621ACDWBR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 22/60页 |
| 文件大小： | 0K |
| 描述： | IC SW QUAD HB/TRPL HISID 54-SOIC |
| 标准包装： | 1,000 |
| 应用： | 自动镜像控制 |
| 核心处理器： | HC08 |
| 程序存储器类型： | 闪存（16 kB） |
| 控制器系列： | 908E |
| RAM 容量： | 512 x 8 |
| 接口： | SCI，SPI |
| 输入/输出数： | 12 |
| 电源电压： | 9 V ~ 16 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 54-SOICW-EP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET SOURCE
High Temperature Reset
The device is protected against high temperature. When
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by the HTR bit in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
The HTR can be disabled by bit HTRD in the Interrupt
Mask register.
Note: Disabling the high temperature reset can lead to
destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
Watchdog Reset
The watchdog module generates a reset, because of a
watchdog timeout or wrong watchdog timer reset. Reset is
flagged by the WDR bit in the Reset Status Register. A
watchdog reset event will reset all registers in the SPI
excluding the RSR.
Main VREG Low Voltage Reset
The LVR is related to the Main VDD. If the voltage falls
below a certain threshold, it will pull down the RST_A pin.
Reset is flagged by the LVR bit in the Reset Status Register.
An LVR event will reset all register in the SPI excluding the
RSR.
Power On Reset
The POR is related to the internal 5.0 V supply. If the
device detects a power on, the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all register
in the SPI including the RSR and set the POR bit.
The Power On Reset circuitry will force the RST_A pin low
for tRST after the VDD has reached its nominal value (above
Reset Pin / External Reset
An external reset can be applied by pulling down the
RST_A pin. The reset event is flagged by the PINR bit in the
reset status register.
Reset Status Register
This register contains five flags that shows the source of
the last reset. A power-on-reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a power-
on-reset or by software.
In addition, the register includes two flags which will
indicate the source of a wake-up from Sleep mode: Either LIN
bus activity, or an event on the L0 wake-up input pin.
POR— Power On Reset bit
This read/write bit is set after power on. Bit is cleared by
writing a logic “1” to this location.
1 = Reset due to power on
0 = no power on reset
PINR— Reset Forced from External Reset Pin Bit
This read/write bit is set after a reset was forced on the
external reset RST_A pin. The bit is cleared by writing an
logic “1” to this location.
1 = reset source is external reset pin
0 = no external reset
WDR— Watch Dog Reset Bit
This read/write flag is set due to a watchdog timeout or
wrong watchdog timer reset. Clear WDR by writing a logic “1”
to WDR.
1 = reset source is watchdog
0 = no watchdog reset
HTR— High Temperature Reset Bit
This read/write bit is set if the chip temperature exceeds a
certain value. The bit is cleared by writing a logic “1” to this
location.
1 = reset due to high temperature condition
0 = no high temperature reset
LVR— Low Voltage Reset Bit
This read/write bit is set if the external VDD voltage coming
from the main voltage regulator falls below a certain value.
The bit is cleared by writing a logic “1” to this location.
1 = reset due to low voltage condition
0 = no low voltage reset
LINWF— LIN Wake-up Flag
This read/write bit is set if a bus activity was the case of an
wake-up. The bit is cleared by writing a logic “1” to this
location.
1 = Wake-up due to bus activity
0 = no wake-up due to bus activity
L0WF— L0 Wake-up Flag
This read/write bit is set if a event on the L0 pin caused an
wake-up. The bit is cleared by writing a logic “1” to this
location.
Register Name and Address: RSR - $0D
Bit7
6
5
4
3
2
1
Bit0
Read
POR
PINR
WDR
HTR
LVR
0
LINWF LOWF
Write
POR
1
0
相关PDF资料 |
PDF描述 |
|---|---|
| MM908E622ACEK | IC HALF-BRIDGE QUAD 54-SOIC |
| MM908E624ACEWR2 | IC SWITCH TRPL HI MCU/LIN 54SOIC |
| MM908E625ACDWB | IC QUAD HALF BRDG MCU/LIN 54SOIC |
| MM908E626AVDWB | IC STEPPER MOTOR DRIVER 54-SOIC |
| MM912F634BV1AER2 | IC MCU 16BIT 32KB FLASH 48LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MM908E621ACPEK | 功能描述:8位微控制器 -MCU QUAD H-B/3-HS W/MCU & LI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MM908E621ACPEKR2 | 功能描述:8位微控制器 -MCU QUAD HB AND TRIPLE HS RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MM908E622 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror |
| MM908E622_08 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-bridge, Triple High Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror |
| MM908E622ACDR2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror |
发布紧急采购，3分钟左右您将得到回复。