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参数资料
| 型号： | MPC5200VR466BR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 466 MHz, MICROPROCESSOR, PBGA272 |
| 封装： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件页数： | 66/80页 |
| 文件大小： | 788K |
| 代理商： | MPC5200VR466BR2 |
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System Design Information
MPC5200B Data Sheet, Rev. 0.6
Freescale Semiconductor
69
Figure 51. Supply Voltage Sequencing
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down
sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
5.1.1
Power Up Sequence
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads
will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance
state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must
power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4
V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection
clamp diodes.
The recommended power up sequence is as follows:
Use one microsecond or slower rise time for all supplies.
VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for
the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way
to accomplish this is to use a low drop-out voltage regulator.
1.5V
2.5V
3.3V
0
DC
Pow
er
Supply
V
o
ltage
VDD_IO,
VDD_IO_MEM (SDR)
VDD_IO_MEM (DDR)
VDD_CORE,
PLL_AVDD
Note:
1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more
than 0.4 V at any time, including power-up.
2. It is recommended that VDD_CORE/PLL_AVDD should track
VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps.
3. Input voltage must not be greater than the supply voltage (VDD_IO)
VDD_IO_MEM, VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time,
1
2
Time
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