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参数资料
| 型号： | MPC5200VR466BR2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 466 MHz, MICROPROCESSOR, PBGA272 |
| 封装： | 27 X 27 MM, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-272 |
| 文件页数： | 80/80页 |
| 文件大小： | 788K |
| 代理商： | MPC5200VR466BR2 |
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Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 0.6
Freescale Semiconductor
9
3.1.4
Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to
high-static voltage or electrical fields. However, it is advised that normal
precautions be taken to avoid application of any voltages higher than
maximum-rated voltages. Operational reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (i.e., either GND or
3.1.5
Power Dissipation
Power dissipation of the MPC5200B is caused by 3 different components: the dissipation of the internal
or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by
SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by
VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation
figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can
not be given in general, but must be calculated by the user for each application case using the following
formula:
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the
IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage.
The total power consumption of the MPC5200B processor must not exceed the value, which would cause
the maximum junction temperature to be exceeded.
Eqn. 2
Table 5. ESD and Latch-Up Protection Characteristics
Sym
Rating
Min
Max
Unit
SpecID
VHBM
Human Body Model (HBM)—JEDEC JESD22-A114-B
2000
—
V
D4.1
VMM
Machine Model (MM)—JEDEC JESD22-A115
200
—
V
D4.2
VCDM
Charge Device Model (CDM)—JEDEC JESD22-C101
500
—
V
D4.3
ILAT
Latch-up Current at TA=85
oC
positive
negative
+100
-100
—mA
D4.4
ILAT
Latch-up Current at TA=27
oC
positive
negative
+200
-200
—mA
D4.5
PIO PIOint
N
M
∑
+
CVDD_IO
2
f
×
=
Ptotal
Pcore Panalog PIO
++
=
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