参数资料
型号: MPC8245LZU266D
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.27 MM PITCH, TBGA-352
文件页数: 19/64页
文件大小: 893K
代理商: MPC8245LZU266D
26
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
1.4.3.4
I2C AC Timing Specifications
Table 12 provides the I2C input AC timing specifications for the MPC8245 at recommended operating
conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
Table 12. I2C Input AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
4.0
CLKs
1, 2
2
Clock low period
(time before the MPC8245 will drive SCL
low as a transmitting slave after detecting
SCL low as driven by an external master)
8.0 + (16
× 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
CLKs
1, 2, 4, 5
3
SCL/SDA rise time (from 0.5 V to 2.4 V)
1
ms
4
Data hold time
0
ns
2
5
SCL/SDA fall time (from 2.4 V to 0.5 V)
1
ms
6
Clock high period
(time needed to either receive a data bit or
generate a START or STOP)
5.0
CLKs
1, 2, 5
7
Data setup time
3.0
ns
3
8
Start condition setup time (for repeated
start condition only)
4.0
CLKs
1,2
9
Stop condition setup time
4.0
CLKs
1, 2
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The
qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 17 for the I2C timing diagram II.
3. Timing is relative to the sampling clock (not SCL).
4. FDR[x] refers to the frequency divider register I2CFDR bit x.
5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR)
determine the maximum I2C input frequency. See Table 13 for more information.
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