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参数资料
| 型号： | MPC8245LZU266D |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.27 MM PITCH, TBGA-352 |
| 文件页数： | 35/64页 |
| 文件大小： | 893K |
| 代理商： | MPC8245LZU266D |
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40
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
PLL Configurations
1.6
PLL Configurations
The internal PLLs of the MPC8245 are configured by the PLL_CFG[0:4] signals. For a given
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory
bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e
CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL
DA[14:15]
F1 J2
Output
GVDD
DRV_MEM_CTRL
2, 6
Notes:
1.
Place a pull-up resistor of 120
or less on the TEST0 pin.
2.
Treat these pins as no connects (NC) unless using debug address functionality.
3.
This pin has an internal pull-up resistor that is enabled only when the MPC8245 is in the reset state. The value of
the internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits
during reset if the signal is left unterminated.
4.
This pin is a reset configuration pin.
5.
DL[0] is a reset configuration pin and has an internal pull-up resistor that is enabled only when the MPC8245 is in
the reset state. The value of the internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1
is read into configuration bits during reset.
6.
Multi-pin signals such as AD[31:0] and MDL[0:31] have their physical package pin numbers listed in order
corresponding to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22,..., AD31 is on pin V25.
7.
GNT4 is a reset configuration pin and has an internal pull-up resistor that is enabled only when the MPC8245 is
in the reset state.
8.
Recommend a weak pull-up resistor (2–10 k
) be placed on this PCI control pin to LVDD.
9.
10. Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to OVDD.
11. Recommend a weak pull-up resistor (2–10 k
) be placed on this pin to GVDD.
12. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not
guaranteed but is sufficient to prevent unused inputs from floating.
13. External PCI clocking source or fan-out buffer may be required for system if using the MPC8245 DUART
functionality since PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.
14. This pin is a multiplexed signal and appears more than once in this table.
15. This pin is affected by programmable PCI_HOLD_DEL parameter.
16. This pin is an open-drain signal.
17. This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open-drain.
18. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.
19. OSC_IN utilizes the 3.3-V PCI interface driver which is 5-V tolerant, see Table 2 for details.
20. PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU and HRST_CTRL.
21. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals
use DRV_MEM_CLK for chip Rev 1.2 (B).
22. The 266- and 300-MHz part offerings can be run at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Note that
source voltage should be 2.0 ± 100 mV for 333- and 350-MHz parts.
23. This pin was formally LAVDD on the MPC8240. It is a NC on the MPC8245. This should not pose a problem when
replacing an MPC8240 with an MPC8245.
24. The driver capability of this pin is hardwired to 40
and cannot be changed.
25. It is recommend that a weak pull-up resistor (2–10 k
) be placed on this pin to OVDD so that a 1 may be detected
at reset if an external memory clock is not being used and PLL[0:4] does not select a half-clock frequency ratio.
Table 17. MPC8245 Pinout Listing (continued)
Name
Pin Numbers
Type
Power
Supply
Output
Driver Type
Notes
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