参数资料
型号: MPC8245LZU266D
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.27 MM PITCH, TBGA-352
文件页数: 23/64页
文件大小: 893K
代理商: MPC8245LZU266D
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
3
Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),
memory controller, DMA controller, PIC interrupt controller, a message unit (and I2O interface), and an I
2C
controller. The processor core is a full-featured, high-performance processor with floating-point support,
memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power management
features. The integration reduces the overall packaging requirements and the number of discrete devices
required for an embedded system.
The MPC8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade-off performance for
power consumption. The processor core is clocked from a separate PLL that is referenced to the peripheral
logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies
while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on
memory data bus width) and a 32-bit address bus along with control signals that enable the interface
between the processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8245
memory space are passed to the processor bus for snooping when snoop mode is enabled.
The processor core and peripheral logic are general-purpose in order to serve a variety of embedded
applications. The MPC8245 can be used as either a PCI host or PCI agent controller.
1.2
Features
Major features of the MPC8245 are as follows:
Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways
— Dynamic power management—Supports 60x nap, doze, and sleep modes
Peripheral logic
— Peripheral logic bus
– Supports various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Supports full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Supports up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– Supports one to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
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