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| 型号： | MPC8306CVMADDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369 |
| 文件页数： | 27/76页 |
| 文件大小： | 474K |
| 代理商： | MPC8306CVMADDCA |
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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
33
HDLC
Figure 22 provides the AC test load.
Figure 22. AC Test Load
Figure 23 and Figure 24 represent the AC timing from Table 31. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 23 shows the timing with external clock.
Figure 23. AC Timing (External Clock) Diagram
Outputs—External clock high impedance
tHEKHOX
18
ns
Inputs—Internal clock input setup time
tHIIVKH
9—
ns
Inputs—External clock input setup time
tHEIVKH
4—
ns
Inputs—Internal clock input hold time
tHIIXKH
0—
ns
Inputs—External clock input hold time
tHEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 31. HDLC AC Timing Specifications1 (continued)
Characteristic
Symbol2
Min
Max
Unit
Output
Z0 = 50
OVDD/2
RL = 50
Serial CLK (Input)
tHEIXKH
tHEIVKH
tHEKHOV
Input Signals:
(See Note)
Output Signals:
(See Note)
Note:
The clock edge is selectable.
tHEKHOX
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