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参数资料
| 型号： | MPC8306CVMADDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369 |
| 文件页数： | 32/76页 |
| 文件大小： | 474K |
| 代理商： | MPC8306CVMADDCA |
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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
38
Freescale Semiconductor
eSDHC
Figure 27 provides the eSDHC clock input timing diagram.
Figure 27. eSDHC Clock Input Timing Diagram
Figure 28 provides the data and command input/output timing diagram.
Figure 28. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock
Input hold times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIXKH
2.5
—
ns
3, 4
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
tSHSKHOV
–3
3
ns
4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV
symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the
output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
2. In full-speed mode, the clock freqency value can be 0–25 MHz for an SD/SDIO card and 0–20 MHz for an MMC card. In
high-speed mode, the clock freqency value can be 0–33.25 MHz for an SD/SDIO card and 0–52 MHz for an MMC card.
3. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4. CCARD 10 pF, (1 card), and CL = CBUS + CHOST +CCARD 40 pF
Table 37. eSDHC AC Timing Specifications (continued)
At recommended operating conditions with OVDD =3.3 V
Parameter
Symbol1
Min
Max
Unit
Notes
eSDHC
tSHSCKR
External Clock
VM
tSHSCK
tSHSCKF
VM = Midpoint Voltage (OVDD/2)
operational mode
tSHSCKL
tSHSCKH
VM = Midpoint Voltage (OVDD/2)
SD_CK
External Clock
SD_DAT/CMD
VM
Inputs
SD_DAT/CMD
Outputs
tSHSIVKH
tSHSIXKH
tSHSKHOV
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