参数资料
型号: MPC8306CVMADDCA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369
封装: 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369
文件页数: 7/76页
文件大小: 474K
代理商: MPC8306CVMADDCA
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
15
DDR2 SDRAM
6.2
DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1
DDR2 SDRAM Input AC Timing Specifications
Table 14 provides the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V).
Table 15 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA =25°C, VOUT = GVDD 2,
VOUT (peak-to-peak) = 0.2 V.
Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 V± 100mV.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
MVREF – 0.25
V
AC input high voltage
VIH
MVREF + 0.25
V
Table 15. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MDM
tCISKEW
ps
1, 2
266 MHz
–750
750
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute
value of tCISKEW.
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