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参数资料
| 型号： | MPC8306CVMADDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA369 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-369 |
| 文件页数： | 67/76页 |
| 文件大小： | 474K |
| 代理商： | MPC8306CVMADDCA |
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MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
7
Electrical Characteristics
– CSB bus clock
IEEE Std. 1149.1 compliant JTAG boundary scan
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8306. The MPC8306 is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.26
V
—
PLL supply voltage
AVDD1
AVDD2
AVDD3
–0.3 to 1.26
V
—
DDR2 DRAM I/O voltage
GVDD
–0.3 to 1.98
V
—
Local bus, DUART, system control and power management, I2C,
SPI, MII, RMII, MII management, eSDHC, FlexCAN, USB and JTAG
I/O voltage
OVDD
–0.3 to 3.6
V
4
Input voltage
DDR2 DRAM signals
MVIN
–0.3 to (GVDD +0.3)
V
2
DDR2 DRAM reference
MVREF
–0.3 to (GVDD +0.3)
V
2
Local bus, DUART, SYS_CLK_IN,
system control and power
management, I2C, SPI, and JTAG
signals
OVIN
–0.3 to (OVDD +0.3)
V
3
Storage temperature range
TSTG
–55to150
C—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
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