参数资料
型号: MPC8377E-RDBA
厂商: Freescale Semiconductor
文件页数: 14/127页
文件大小: 0K
描述: BOARD REF DES MPC8377 REV 2.1
设计资源: MPC8379E-RDB Ref Design Guide
标准包装: 1
系列: PowerQUICC II™ PRO
类型: MPU
适用于相关产品: MPC8377E
所含物品: 板,CD
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
110
Freescale Semiconductor
23.1
System PLL Configuration
The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency
depends on RCWLR[DDRCM] and RCWLR[LBCM]. Table 75 shows the multiplication factor encodings
for the system PLL.
NOTE
If RCWLR[DDRCM] and RCWLR[LBCM] are both cleared, the system
PLL VCO frequency = (CSB frequency)
× (System PLL VCO Divider).
If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL
VCO frequency = 2
× (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MHz.
As described in Section 23, “Clocking,The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 77
and Table 78 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 76.
Table 75. System PLL Multiplication Factors
RCWLR[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
× 7 to × 15
Table 76. System PLL VCO Divider
RCWLR[SVCOD]
VCO Division Factor
00
4
01
8
10
2
11
1
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