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| 型号： | MPC8379E-MDS-PB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 49/117页 |
| 文件大小： | 0K |
| 描述： | BOARD PROCESSOR FOR MDS S |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MPU |
| 适用于相关产品： | MPC8379 |
| 所含物品： | 板 |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
37
This table describes the general timing parameters of the local bus interface of the device when in PLL
bypass mode.
This figure provides the AC test load for the local bus.
Figure 19. Local Bus AC Test Load
Table 40. Local Bus General Timing Parameters—PLL Bypass Mode
Parameter
Symbol1
Min
Max
Unit
Note
Local bus cycle time
tLBK
15
—
ns
Input setup to local bus clock
tLBIVKH
7.0
—
ns
Input hold from local bus clock
tLBIXKH
1.0
—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3.0
—
ns
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
Local bus clock to LALE rise
tLBKHLR
—4.5
ns
—
Local bus clock to output valid
tLBKHOV
—3.0
ns
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
4.0
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from LBVDD/2 of the rising/falling edge of LCLK0 to 0.4 × LBVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load
on LAD output pins.
7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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