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| 型号： | MPC8379E-MDS-PB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 87/117页 |
| 文件大小： | 0K |
| 描述： | BOARD PROCESSOR FOR MDS S |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MPU |
| 适用于相关产品： | MPC8379 |
| 所含物品： | 板 |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
71
— The SerDes reference clock input can be either differential or single-ended. Refer to the
Differential Mode and Single-ended Mode description below for further detailed requirements.
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V
÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50
Ω to
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
The input amplitude requirement
— This requirement is described in detail in the following sections.
Figure 49. Receiver of SerDes Reference Clocks
20.2.2
DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the device SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
Input
Amp
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
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相关代理商/技术参数 |
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| MPC8379E-RDB | 功能描述:网络控制器与处理器 IC REF BRD FOR MPC837 RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| MPC8379E-RDBA | 功能描述:开发板和工具包 - 其他处理器 MPC8379E REF DESIGN BD RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| MPC8379E-RDBA | 制造商:Freescale Semiconductor 功能描述:MPC8379E-RDB Reference Platform |
| MPC8379EVRAFDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EVRAFFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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