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型号： MPC8544EAVTAQGA
厂商： Freescale Semiconductor
文件页数： 32/117页
文件大小： 0K
描述： IC MPU POWERQUICC III 783-FCBGA
标准包装： 36
系列： MPC85xx
处理器类型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
电压： 0.95 V ~ 1.05 V
安装类型： 表面贴装
封装/外壳： 783-BBGA，FCBGA
供应商设备封装： 783-FCPBGA（29x29）
包装： 托盘
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
21
DDR and DDR2 SDRAM
NOTE
For the ADDR/CMD setup and hold specifications in Table 18, it is assumed
that the clock control register is set to adjust the memory clocks by
applied cycle.
Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
Figure 4. Timing Diagram for tDDKHMH
MDQS postamble
tDDKHME
0.4 x tMCK
0.6 x tMCK
ns
6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock
adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been
set to the same adjustment value. See the MPC8544E PowerQUICC III Integrated Communications Processor Reference
Manual, for a description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
7. Maximum DDR1 frequency is 400 MHz.
Table 18. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions.
Parameter
Symbol1
Min
Max
Unit
Notes
MDQS
MCK[n]
tMCK
MDQS
tDDKHMH(max) = 0.6 ns
tDDKHMH(min) = –0.6 ns
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