参数资料
型号: MPC8572CPXAUNB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
封装: 33 X 33 MM, PLASTIC, FCBGA-1023
文件页数: 123/138页
文件大小: 1502K
代理商: MPC8572CPXAUNB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
85
PCI Express
TTX-IDLE-TO-DIFF-DATA Maximum time to
transition to valid
TX specifications
after leaving an
Electrical idle
condition
20
UI
Maximum time to meet all TX specifications when
transitioning from Electrical Idle to sending
differential data. This is considered a debounce
time for the TX to meet all TX specifications after
leaving Electrical Idle
RLTX-DIFF
Differential
Return Loss
12
dB
Measured over 50 MHz to 1.25 GHz. See Note 4
RLTX-CM
Common Mode
Return Loss
6
dB
Measured over 50 MHz to 1.25 GHz. See Note 4
ZTX-DIFF-DC
DC Differential
TX Impedance
80
100
120
Ω
TX DC Differential mode Low Impedance
ZTX-DC
Transmitter DC
Impedance
40
Ω
Required TX D+ as well as D- DC Impedance
during all states
LTX-SKEW
Lane-to-Lane
Output Skew
500 +
2 UI
ps
Static skew between any two Transmitter Lanes
within a single Link
CTX
AC Coupling
Capacitor
75
200
nF
All Transmitters shall be AC coupled. The AC
coupling is required either within the media or within
the transmitting component itself. See Note 8.
Tcrosslink
Crosslink
Random
Timeout
0
1
ms
This random timeout helps resolve conflicts in
crosslink configuration by eventually resulting in
only one Downstream and one Upstream Port. See
Note 7.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 57 and measured over
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 55.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
Transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The Transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 ohms to ground for both the D+
and D- line (that is, as measured by a Vector Network Analyzer with 50 ohm probes—see Figure 57). Note that the series
capacitors CTX is optional for the return loss measurement.
5. Measured between 20-80% at transmitter package pins into a test load as shown in Figure 57 for both VTX-D+ and VTX-D-.
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a.
8. MPC8572E SerDes transmitter does not have CTX built-in. An external AC Coupling capacitor is required.
Table 59. Differential Transmitter (TX) Output Specifications (continued)
Symbol
Parameter
Min
Nominal
Max
Units
Comments
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