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| 型号： | MPC8572CPXAUNB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023 |
| 封装： | 33 X 33 MM, PLASTIC, FCBGA-1023 |
| 文件页数： | 30/138页 |
| 文件大小： | 1502K |
| 代理商： | MPC8572CPXAUNB |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
125
System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8572E.
21.1
System Clocking
This device includes seven PLLs, as follows:
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.”
2. There are two core PLLs whose ratios are individually configurable. Each e500 core PLL
generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as
described in Section 19.3, “e500 Core PLL Ratio.”
3. The DDR Complex PLL generates the clocking for the DDR Controllers
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes1 block to be used for PCI Express and Serial Rapid IO Interfaces.
6. There is a PLL for the SerDes2 block to be used for SGMII Interface.
21.2
Power Supply Design
21.2.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CORE0, AVDD_CORE1, AVDD_DDR, AVDD_LBIU, AVDD_SRDS1 and
AVDD_SRDS2 respectively). The AVDD level should always be equivalent to VDD, and preferably these
voltages will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 62, one to each of the
AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 1023 FC-PBGA footprint, without the inductance of vias.
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相关代理商/技术参数 |
参数描述 |
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| MPC8572CVTAVNE | 功能描述:微处理器 - MPU R211 NoE NoPb 1500 Ext RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8572DS | 功能描述:开发板和工具包 - 其他处理器 MICRO-ATX HIGH PERFORMAN RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
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