参数资料
型号: MPC8572CPXAUNB
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
封装: 33 X 33 MM, PLASTIC, FCBGA-1023
文件页数: 78/138页
文件大小: 1502K
代理商: MPC8572CPXAUNB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead,
SerDes reference clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
8.3.1
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clock are described in
8.3.2
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
Table 36 lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and
SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
Table 36. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
tREF
REFCLK cycle time
10 (8)
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
——
100
ps
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge
location
–50
50
ps
Note:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.
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