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| 型号： | MPC9315AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 4:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9315 REVISION 5 JANUARY 24, 2013
3
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
Table 1. Pin Configuration
Pin
I/O
Type
Function
CLK0
Input
LVCMOS
Reference clock input
CLK1
Input
LVCMOS
Alternative clock input
FB0
Input
LVCMOS
PLL feedback input
FB1
Input
LVCMOS
Alternative feedback input
REF_SEL
Input
LVCMOS
Selects clock input reference clock input, default low (pull-down)
FB_SEL
Input
LVCMOS
Selects PLL feedback clock input, default low (pull-down)
FSELA
Input
LVCMOS
Selects divider ratio of bank A outputs, default low (pull-down)
FSELB
Input
LVCMOS
Selects divider ratio of bank B outputs, default low (pull-up)
FSELC
Input
LVCMOS
Selects divider ratio of bank C outputs, default low (pull-up)
PSELA
Input
LVCMOS
Selects phase of bank A outputs
QA0, QA1
Output
LVCMOS
Bank A outputs
QB0 to QB3
Output
LVCMOS
Bank B outputs
QC0, QC1
Output
LVCMOS
Bank C outputs
OE
Input
LVCMOS
Output tristate
VCCA
Supply
Analog (PLL) positive supply voltage. Requires external RC filter
VCC
Supply
Digital positive supply voltage
GND
Ground
Digital negative supply voltage (ground)
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
CLK0
CLK1
FB_SEL
0
FB0
FB1
FSELA
0
QAx = VCO clock frequency
QA0, QA1 = VCO clock frequency
2
FSELB
1
QBx = VCO clock frequency
QB0 - QB3 = VCO clock frequency
2
FSELC
1
QCx = VCO clock frequency
2
QC0, QC1 = VCO clock frequency
4
PSELA
0
0° (QA0, QA1 non-inverted)
180
(QA0, QA1 inverted)
VCCA
none
VCCA = GND, PLL off and bypassed for static test and diagnosis VCCA = 3.3 or 2.5 V, PLL enabled
MR
0
Normal operation
Reset (VCO clamped to min. range)
OE
0
Outputs enabled
Outputs disabled (tristate), open PLL loop
Table 3. Absolute Maximum Ratings(1)
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under
absolute-maximum-rated conditions is not implied.
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
4.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
VOUT
DC Output Voltage
-0.3
VCC+0.3
V
IIN
DC Input Current
20
mA
IOUT
DC Output Current
50
mA
TS
Storage temperature
-55
125
C
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