参数资料
型号: MPC9315AC
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/18页
文件大小: 0K
描述: IC PLL CLOCK GEN/DRIVER 32-LQFP
标准包装: 250
类型: PLL 时钟发生器
PLL:
输入: LVCMOS
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 4:8
差分 - 输入:输出: 无/无
频率 - 最大: 160MHz
除法器/乘法器: 是/是
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-TQFP(7x7)
包装: 托盘
MPC9315 REVISION 5 JANUARY 24, 2013
12
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
Figure 15. Propagation delay (t(), SPO) Test Reference
Figure 16. Output Duty Cycle (DC)
Figure 17. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCC 2
GND
VCC
VCC 2
GND
tSK(O)
VCC
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCC 2
GND
VCC
VCC 2
GND
t()
CLK0, 1
FB0, 1
VCC
Figure 18. Cycle-to-Cycle Jitter
Figure 19. Period Jitter
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles
TN
TN+1
TJIT(PER) = |TN–1/f0|
T0
tF
tR
VCC=3.3 V
VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
Figure 20. I/O Jitter
Figure 21. Output Transition Time Test Reference
TJIT() = |T0–T1mean|
TCLK0, 1
FB0, 1
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles
TJIT(CC) = |TN–TN+1|
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