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参数资料
| 型号： | MPC9315AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 14/18页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 4:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9315 REVISION 5 JANUARY 24, 2013
5
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40° to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
1 feedback
2 feedback
4 feedback
PLL bypass mode
100(2)
37.50
18.75
0
2. The VCO range in
1 feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100 fVCO 160 MHz. Please see
next revision of the MPC9315 for improved VCO frequency range.
160
80
40
TBD
MHz
PLL locked
VCCA = GND
fVCO
VCO Lock Range
75(2)
160
MHz
fMAX
Maximum Output Frequency
1 output
2 output
4 output
75
37.50
18.75
160
80
40
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
CLK0, CLK1 Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay
CLK0 or CLK1 to FB
(Static Phase Offset)
-150
+150
ps
PLL locked
tSK()
Output-to-Output Skew
Within one bank
Any output
80
120
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
BW
PLL closed loop bandwidth
1 feedback
2 feedback
4 feedback
TBD
2.0 - 20
0.6 - 6.0
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
(1
)
10
22
ps
RMS value
tJIT(PER)
Period Jitter
(1
)
8.0
15
ps
RMS value
tJIT()
I/O Phase Jitter
(1
)
8.0 - 25(3)
3. I/O jitter depends on VCO frequency. Please see Applications Information section for I/O jitter versus VCO frequency characteristics.
TBD
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = -40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH = –15
mA(1)
1. The MPC9315 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
VOL
Output Low Voltage
0.6
V
IOL= 15 mA
ZOUT
Output Impedance
17 - 20
IIN
Input Current(2)
2. Inputs have pull-up or pull-down resistors affecting the input current.
200
A
VIN = VCC or
GND
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
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