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| 型号： | MPC9315AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 16/18页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 4:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9315 REVISION 5 JANUARY 24, 2013
7
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
APPLICATIONS INFORMATION
Programming the MPC9315
The PLL of the MPC9315 supports output clock
frequencies from 18.75 to 160 MHz. Different feedback and
output divider configurations can be used to achieve the
desired input to output frequency relationship. The feedback
frequency and divider should be used to situate the VCO in
the frequency range between 75 and 160 MHz for stable and
optimal operation. The FSELA, FSELB, FSELC pins select
the desired output clock frequencies. Possible frequency
ratios of the reference clock input to the outputs are 1:1, 1:2,
illustrate the various output configurations and frequency
ratios supported by the MPC9315. PSELA controls the output
phase of the QA0 and QA1 outputs, allowing the user to
generate inverted clock signals synchronous to non-inverted
clock signals. See also Example Configurations for the
MPC9315 for further reference.
Table 9. Output Frequency Relationship for QA0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
2
0
1
CLK
4
0
1
0
CLK
2
CLK
2
0
1
CLK
2
CLK
4
1
0
CLK
2 * CLK
CLK
1
0
1
CLK
2 * CLK
CLK
2
1
0
CLK
1
CLK
2
Table 10. Output Frequency Relationship for QB0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
2
0
1
CLK
4
0
1
0
2 * CLK
CLK
0
1
2 * CLK
CLK
2
1
0
CLK
2
CLK
2
1
0
1
CLK
2
CLK
4
1
0
CLK
1
CLK
2
Table 11. Output Frequency Relationship for QC0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
2 * CLK
CLK
0
1
4 * CLK
CLK
0
1
0
2 * CLK
CLK
0
1
4 * CLK
2 * CLK
CLK
1
0
CLK
2 * CLK
CLK
1
0
1
2 * CLK
4 * CLK
CLK
1
0
CLK
1
2 * CLK
CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9315ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9315FA | 功能描述:锁相环 - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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