- 您现在的位置：买卖IC网 > PDF目录2099 > MPC9315AC (IDT, Integrated Device Technology Inc)IC PLL CLOCK GEN/DRIVER 32-LQFP PDF资料下载
参数资料
| 型号： | MPC9315AC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 18/18页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| 标准包装： | 250 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 4:8 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 160MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC9315 REVISION 5 JANUARY 24, 2013
9
2013 Integrated Device Technology, Inc.
MPC9315 DATA SHEET
2.5 V AND 3.3 V CMOS PLL CLOCK GENERATOR AND DRIVER
Using the MPC9315 in Zero-Delay Applications
The external feedback option of the MPC9315 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the
MPC9315 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Calculation of Part-to-Part Skew
The MPC9315 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9315 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 7. MPC9315 max. Device-to-Device Skew
Due to the statistical nature of I/O jitter, an RMS value (1
)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 12.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (
3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –300 ps to +300 ps relative to TCLK (VCC =3.3 V
and fVCO = 160 MHz):
tSK(PP) = [–150ps...150ps] + [–150ps...150ps] +
[(10ps @ –3)...(10ps @ 3)] + tPD, LINE(FB)
tSK(PP) = [–300ps...300ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC = 3.3 V (10 ps
RMS). I/O jitter is frequency-dependant with a maximum at
the lowest VCO frequency (160 MHz for the MPC9315).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and for
part-to-part skew tSK(PP).
Figure 8. Max. I/O Jitter (RMS) versus
Frequency for VCC = 2.5 V
Figure 9. Max. I/O Jitter (RMS) versus
Frequency for VCC = 3.3 V
Table 12. Confidence Factor CF
CF
Probability of Clock Edge within the Distribution
1
0.68268948
2
0.95449988
3
0.99730007
4
0.99993663
5
0.99999943
6
0.99999999
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
TCLKCOMMON
30
25
20
15
10
5
0
75
100
125
150
175
200
VCO frequency [MHz]
t JI
T()
[p
s]
ms
I/O Jitter (RMS) versus VCO frequency
30
25
20
15
10
5
0
75
100
125
150
175
200
t JI
T(
)
[p
s]
ms
I/O Jitter (RMS) versus VCO frequency
VCO frequency (MHz)
相关PDF资料 |
PDF描述 |
|---|---|
| MPC9350AC | IC PLL CLOCK DRIVER LV 32-LQFP |
| MPC941AE | IC CLOCK BUFFER MUX 1:27 48-LQFP |
| MPC9443FAR2 | IC CLK BUFF DVDR MUX 3:16 48LQFP |
| MPC9446FAR2 | IC CLK BUFF DVDR MUX 2:10 32LQFP |
| MPC9447ACR2 | IC CLOCK BUFFER MUX 2:9 32-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC9315ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9315FA | 功能描述:锁相环 - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。