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参数资料
| 型号： | MPC961PAC |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER ZD 1:18 PLL 32-LQFP |
| 标准包装： | 250 |
| 类型： | 零延迟缓冲器 |
| PLL： | 是 |
| 输入： | LVPECL |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:17 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
MPC961P REVISION 5 JANUARY 8, 2013
7
2013 Integrated Device Technology, Inc.
MPC961P Data Sheet
LOW VOLTAGE ZERO DELAY BUFFER
the line impedances. The voltage wave launched down the
two lines will equal:
VL =VS (ZO / (RS + RO + ZO))
ZO =50 || 50
RS =36 || 36
RO =14
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
=1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 5. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 6. Optimized Dual Line Termination
SPICE level and IBIS output buffer models are available
for engineers who want to simulate their specific interconnect
schemes.
Using the MPC961P in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC961P. Designs using the MPC961P as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC961P clock driver allows for its use as a zero delay
buffer. By using the QFB output as a feedback to the PLL the
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device. The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter),
feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC961P zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC961P are connected together, the maximum overall
timing uncertainty from the common PCLK input to any output
is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 7. MPC961P Max. Device-to-Device Skew
Due statistical nature of I/O jitter a rms value (1
) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
TIME (ns)
VO
LTAGE
(V
)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC961
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
= 25
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
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