参数资料
型号: MSC8101VT1250F
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封装: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件页数: 56/104页
文件大小: 1811K
代理商: MSC8101VT1250F
AC Timings
MSC8101 Technical Data, Rev. 18
Freescale Semiconductor
2-15
35c
BG delay from the 50% level of the DLLIN rising edge
1.0
4.0
5.5
ns
35d
TS delay from the 50% level of the DLLIN rising edge
1.0
3.5
5.0
ns
36
Delay from the 50% level of the DLLIN rising edge for all other signals
1.0
4.5
6.0
ns
Notes:
1.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8101 device, the frequency is determined by adding the input and output
longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when
connected to another MSC8101 device, the frequency is determined by adding the input and output longest timing values,
which results in a frequency of 75 MHz for 30 pF output capacitance.
Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus
frequencies.
In single-master mode, the frequency depends on the timing of the devices connected to the MSC8101.
2.
Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
Table 2-17.
AC Timing for SIU Outputs
No.
Characteristic
Min.
Maximum2
Units
30 pF
50 pF
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