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参数资料
| 型号： | MSC8144VT1000B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 29/80页 |
| 文件大小： | 1250K |
| 代理商： | MSC8144VT1000B |
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Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
35
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.6.1
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.2
describes the clocking characteristics. Section 2.6.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144 device:
PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V)
supply. See Table 19 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.
During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.
Note:
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after
power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows
during power-up.
Figure 6 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
2.6.2
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 16 shows the maximum frequency values for
CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded.
Figure 6. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO
Table 16. Clock Frequencies
Characteristic
Symbol
Min
Max
Unit
CLKIN frequency
FCLKIN
33
133
MHz
PCI_CLK_IN frequency
FPCI_CLK_IN
33
133
MHz
CLKIN duty cycle
DCLKIN
40
60
%
PCI_CLK_IN duty cycle
DPCI_CLK_IN
40
60
%
Vo
lt
a
g
e
Time
3.3 V
VDDIO Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET
1
VDDIO applied
1.0 V
VDDIO = Nominal
VDD = Nominal
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| MSC8144VT800B | 制造商:Freescale Semiconductor 功能描述:DSP 32-Bit 800MHz 800MIPS 783-Pin FCBGA 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC81450M | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS |
| MSC8151 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Single-Core Digital Signal Processor |
| MSC8151SAG1000B | 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Bulk 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 1X 1GHZ SC3850 783FCBGA |
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