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| 型号： | MSC8144VT1000B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 58/80页 |
| 文件大小： | 1250K |
| 代理商： | MSC8144VT1000B |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
61
2.6.12
SPI Timing
Table 48 lists the SPI input and output AC timing specifications.
Figure 34 provides the AC test load for the SPI.
Figure 34. SPI AC Test Load
Figure 35 and Figure 36 represent the AC timings from Table 48. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 35 shows the SPI timings in slave mode (external clock).
Figure 35. SPI AC Timing in Slave Mode (External Clock)
Figure 36 shows the SPI timings in master mode (internal clock).
Table 48. SPI AC Timing Specifications 1
Characteristic
Symbol 2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
tNIKHOV
6ns
SPI outputs hold—Master mode (internal clock) delay
tNIKHOX
0.5
ns
SPI outputs valid—Slave mode (external clock) delay
tNEKHOV
8ns
SPI outputs hold—Slave mode (external clock) delay
tNEKHOX
2ns
SPI inputs—Master mode (internal clock input) setup time
tNIIVKH
4ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2ns
Notes:
1.
Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
2.
The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and
t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for
the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
SPICLK (Input)
tNEIXKH
tNEIVKH
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
tNIKHOV
tNIKHOX
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