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参数资料
| 型号： | MSC8144VT1000B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 40/80页 |
| 文件大小： | 1250K |
| 代理商： | MSC8144VT1000B |
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Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
45
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall
entirely within the unshaded portion of the transmitter output compliance mask shown in Figure 12 with the parameters
specified in Table 31 when measured at the output pins of the device and the device is driving a 100
Ω ±5% differential resistive
load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce
inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or
minimized.
Table 29. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage
VO
-0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage
VDIFFPP
800
1600
mVPP
Deterministic Jitter
JD
0.17
UIPP
Total Jitter
JT
0.35
UIPP
Multiple output skew
SMO
1000
ps
Skew at the transmitter output between lanes of a
multilane link
Unit Interval
UI
400
ps
±100 ppm
Table 30. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage
VO
-0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential Output Voltage
VDIFFPP
800
1600
mVPP
Deterministic Jitter
JD
0.17
UIPP
Total Jitter
JT
0.35
UIPP
Multiple output skew
SMO
1000
ps
Skew at the transmitter output between lanes of a
multilane link
Unit Interval
UI
320
ps
±100 ppm
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