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| 型号： | MSC8144VT1000B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 35/80页 |
| 文件大小： | 1250K |
| 代理商： | MSC8144VT1000B |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
40
2.6.4.2
DDR SDRAM Output AC Timing Specifications
Table 23 provides the output AC timing specifications for the DDR SDRAM interface.
Table 23. DDR SDRAM Output AC Timing Specifications
Parameter
Symbol 1
Min
Max
Unit
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)2
tMCK
510
ns
ADDR/CMD output setup with respect to MCK3
400 MHz
333 MHz
266 MHz
200 MHz
tDDKHAS
1.95
2.40
3.15
4.20
—
ns
ADDR/CMD output hold with respect to MCK3
400 MHz
333 MHz
266 MHz
200 MHz
tDDKHAX
1.85
2.40
3.15
4.20
—
ns
MCSn output setup with respect to MCK3
400 MHz
333 MHz
266 MHz
200 MHz
tDDKHCS
1.95
2.40
3.15
4.20
—
ns
MCSn output hold with respect to MCK3
400 MHz
333 MHz
266 MHz
200 MHz
tDDKHCX
1.95
2.40
3.15
4.20
—
ns
MCK to MDQS Skew4
tDDKHMH
–0.6
0.6
ns
MDQ/MECC/MDM output setup with respect to MDQS5
400 MHz
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
700
900
1100
1200
—
ps
MDQ/MECC/MDM output hold with respect to MDQS5
400 MHz
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
700
900
1100
1200
—
ps
MDQS preamble start6
tDDKHMP
–0.5
× tMCK – 0.6
–0.5
× tMCK +0.6
ns
MDQS epilogue end6
tDDKHME
–0.6
0.6
ns
Notes:
1.
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2.
All MCK/MCK referenced measurements are made from the crossing of the two signals
±0.1 V.
3.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by
1/2 applied cycle.
4.
Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MSC8144 Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
5.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6.
All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
7.
At recommended operating conditions with VDDDDR (1.8 V or 2.5 V) ± 5%.
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