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| 型号： | MSC8144VT1000B |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封装： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件页数： | 46/80页 |
| 文件大小： | 1250K |
| 代理商： | MSC8144VT1000B |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
50
2.6.5.8
Eye Template Measurements
For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (baud
frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT)
defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive
directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined
in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0.
The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10–12. The eye pattern
shall be measured with AC coupling and the compliance template centered at 0 Volts differential. The left and right edges of
the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100
Ω
resistive
±5% differential to 2.5 GHz.
2.6.5.9
Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is
applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in
Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and
opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.
Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be
measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance
setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std.
802.3ae.
2.6.5.10
Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100
Ω resistive ±5% differential to 2.5 GHz.
2.6.5.11
Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum
of deterministic and random jitter defined in Section 2.6.5.9 and then adjusting the signal amplitude until the data eye contacts
the 6 points of the minimum eye opening of the receive template shown in Figure 14 and Table 35. Note that for this to occur,
the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using
a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter
specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.6.6
PCI Timing
This section describes the general AC timing parameters of the PCI bus. Table 36 provides the PCI AC timing specifications.
Table 36. PCI AC Timing Specifications
Parameter
Symbol
33 MHz
66 MHz
Unit
Min
Max
Min
Max
Output delay
tPCVAL
2.0
11.0
1.0
6.0
ns
High-Z to Valid Output delay
tPCON
2.0
—
1.0
—
ns
Valid to High-Z Output delay
tPCOFF
—
28
—
14
ns
Input setup
tPCSU
7.0
—
3.0
—
ns
Input hold
tPCH
0—0
—
ns
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