参数资料
型号: MSC8144VT1000B
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 133 MHz, OTHER DSP, PBGA783
封装: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件页数: 64/80页
文件大小: 1250K
代理商: MSC8144VT1000B
Hardware Design Considerations
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
67
3.3
Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
Keep clock and timing signal paths as short as possible and route with 50
Ω impedance.
Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resistor value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
Note:
See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.
3.4
Connectivity Guidelines
Note:
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
GND indicates using a 10 k
Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
2.
VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
3.
Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.
4.
NC indicates “not connected” and means do not connect anything to the pin.
5.
The phrase “in use” indicates a typical pin connection for the required function.
Note:
Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
3.4.1
DDR Memory Related Pins
This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.
Note:
For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines
of strobes in DDR1), please refer to Table 51.
3.4.1.1
DDR Interface Is Not Used
Table 51. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name
Pin Connection
MDQ[0–31]
NC
MDQS[0–3]
NC
MDQS[0–3]
NC
MA[0–15]
NC
MCK[0–2]
NC
MCK[0–2]
NC
MCS[0–1]
NC
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