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| 型号： | MT41J512M4JE-187EIT:A |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, PBGA82 |
| 封装： | 12.50 X 15 MM, LEAD FREE, FBGA-82 |
| 文件页数： | 9/11页 |
| 文件大小： | 288K |
PDF: 09005aef826aaadc/Source: 09005aef826a65af
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2Gb DDR3 SDRAM.fm - Rev. C 12/07 EN
7
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8 DDR3 SDRAM
Mode Register (MR) Definition
Advance
Mode Register (MR) Definition
Mode registers MR0 through MR3 are used to define various modes of programmable
operations of the DDR3 SDRAM. A mode register is programmed via the MODE
REGISTER SET (MRS) command during initialization. It will retain the stored informa-
tion (except for bit MR0[8], which is self-clearing) until either:
It is reprogrammed
RST# goes LOW
The device loses power
Contents of a mode register can be altered by reissuing the MRS command. If the user
chooses to modify only a subset of the mode register’s variables, all variables must be
programmed when the MRS command is issued. Reprogramming the mode register will
not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks are idle and in the
precharged state (tRP has been satisfied and no data bursts are in progress). Once an
MRS command has been issued, tMRD and tMOD must be satisfied.
Figure 3:
Mode Register 0 (MR0) Definition
Notes:
1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.”
01
BL
CAS# latency BT
PD
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode register 0 (MR0)
Address bus
97
6
5
4
3
82
1
0
A10
A12 A11
BA0
BA1
10
11
12
13
M3
0
1
READ Burst Type
Sequential (nibble)
Interleaved
CAS Latency
Reserved
5
6
7
8
9
10
11 (DDR3-1600)
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
15
DLL
Write Recovery
Reserved
5
6
7
8
10
12
Reserved
WR
0
M12
0
1
Precharge PD
DLL off (slow exit)
DLL on (fast exit)
BA2
16
01
Burst Length
Fixed BL8
4 or 8 (on-the-fly via A12)
Fixed BC4 (chop)
Reserved
M0
0
1
0
1
M1
0
1
M9
0
1
0
1
0
1
0
1
M10
0
1
0
1
M11
0
1
M14
0
1
0
1
M15
0
1
Mode Register
Mode register 0 (MR0)
Mode register 1 (MR1)
Mode register 2 (MR2)
Mode register 3 (MR3)
A13
14
01
M8
0
1
DLL Reset
No
Yes
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相关代理商/技术参数 |
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