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参数资料
| 型号： | MT42L128M32D2MH-3 IT:A |
| 厂商： | Micron Technology Inc |
| 文件页数： | 111/164页 |
| 文件大小： | 0K |
| 描述： | IC LPDDR2 SDRAM 4GBIT 134FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR2 SDRAM |
| 存储容量： | 4G（128M x 32） |
| 速度： | 333MHz |
| 接口： | 并联 |
| 电源电压： | 1.14 V ~ 1.3 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 134-VFBGA |
| 供应商设备封装： | 134-FBGA（11x11.5） |
| 包装： | 散装 |
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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Truth Tables
3. Current state definitions:
Idle: The bank has been precharged and t RP has been met.
Active: A row in the bank has been activated, t RCD has been met, no data bursts or ac-
cesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled and the READ has
not yet terminated or been terminated.
Write: A WRITE burst has been initiated with auto precharge disabled and the WRITE
has not yet terminated or been terminated.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. A BST command cannot be issued to another bank; it applies only to the bank represen-
ted by the current state.
6. The states listed below must not be interrupted by any executable command. NOP com-
mands must be applied during each clock cycle while in these states:
Idle MRR: Starts with registration of the MRR command and ends when t MRR has been
met. After t MRR is met, the device is in the all banks idle state.
Reset MRR: Starts with registration of the MRR command and ends when t MRR has been
met. After t MRR is met, the device is in the all banks idle state.
Active MRR: Starts with registration of the MRR command and ends when t MRR has
been met. After t MRR is met, the bank is in the active state.
MRW: Starts with registration of the MRW command and ends when t MRW has been
met. After t MRW is met, the device is in the all banks idle state.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
BST is supported only if a READ or WRITE burst is ongoing.
t RRD must be met between the ACTIVATE command to bank n and any subsequent
ACTIVATE command to bank m .
READs or WRITEs listed in the command column include READs and WRITEs with or
without auto precharge enabled.
This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
MRR is supported in the row-activating state.
MRR is supported in the precharging state.
The next state for bank m depends on the current state of bank m (idle, row-activating,
precharging, or active).
A WRITE command can be issued after the completion of the READ burst; otherwise a
BST must be issued to end the READ prior to asserting a WRITE command.
A READ command can be issued after the completion of the WRITE burst; otherwise, a
BST must be issued to end the WRITE prior to asserting another READ command.
A READ with auto precharge enabled or a WRITE with auto precharge enabled can be
followed by any valid command to other banks provided that the timing restrictions in
the PRECHARGE and Auto Precharge Clarification table are met.
Not bank-specific; requires that all banks are idle and no bursts are in progress.
RESET command is achieved through MODE REGISTER WRITE command.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
111
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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