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参数资料
| 型号： | MT45W2MV16BABB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | LEAD FREE, FBGA-54 |
| 文件页数： | 50/55页 |
| 文件大小： | 816K |
| 代理商： | MT45W2MV16BABB-856WT |
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2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
54
2004 Micron Technology, Inc. All Rights Reserved.
Extended WRITE Timing—
Asynchronous WRITE Operation
Modified timings are required during extended
WRITE operations (see Figure 47 below). An extended
WRITE operation requires that both the write pulse
width (tWP) and the data valid period (tDW) be length-
ened to at least the minimum WRITE cycle time (tWC
[MIN]). These increased timings ensure that time is
available for both a refresh operation and a successful
completion of the WRITE operation.
Figure 47: Extended WRITE Operation
Page Mode READ Operation
When a CellularRAM device is configured for page
mode operation, the address inputs are used to accel-
erate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. If CE# is LOW longer than
the tCEM maximum time of 10s, no refresh will occur
and data may be lost. Page mode should only be used
in systems that can limit CE#-LOW times to less than
10s.
Burst-Mode Operation
When configured for burst-mode operation, it is
necessary to allow the device to perform a refresh
within any 10s window. One of two conditions will
enable the device to schedule a refresh within 10s.
The first condition is when all burst operations com-
plete within 10s. A burst completes when the CE# sig-
nal is registered HIGH on a rising clock edge. The
second condition that allows a refresh is when a burst
access crosses a row boundary. The row-boundary
crossing causes WAIT to be asserted while the next row
is accessed and enables the scheduling of refresh.
Summary
CellularRAM products are designed to ensure that
any possible asynchronous timings do not cause data
corruption due to lack of refresh. Slow bus timings on
asynchronous WRITE operations require that tWP and
tDW be lengthened. Asynchronous page bus timings
must limit CE# LOW to less than 10s.
Burst mode timings must allow the device to per-
form a refresh within any 10s period. A burst opera-
tion must either complete (CE# registered HIGH) or
cross a row boundary within 10s to ensure successful
refresh scheduling. These timing requirements are
likely to have little or no impact when interfacing a
CellularRAM device with a low-speed memory bus.
Data Valid
DATA-IN
ADDRESS
CE#
LB#/UB#
WE#
tCEM or tTM > 10s
tWP
tWC (MIN)
>
tDW
tWC (MIN)
>
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MV16PFA-70 WT | 制造商:Micron Technology Inc 功能描述:2MX16 PSRAM PLASTIC WIRELESS TEMP FBGA 1.8V ASYNCH PSEUDO ST - Trays |
| MT45W2MW16BABB-706 L WT | 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:378 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-CBGA 供应商设备封装:48-CBGA（7x7） 包装:托盘 |
| MT45W2MW16BABB-706 L WT TR | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Tape and Reel |
| MT45W2MW16BABB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM Async 1 32M-Bit 2M x 16 70ns 54-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays 制造商:Micron Technology Inc 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA |
| MT45W2MW16BABB-706 WT TR | 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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