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参数资料
| 型号： | MT45W2MV16BABB-856WT |
| 元件分类： | SRAM |
| 英文描述： | 2M X 16 PSEUDO STATIC RAM, 85 ns, PBGA54 |
| 封装： | LEAD FREE, FBGA-54 |
| 文件页数： | 6/55页 |
| 文件大小： | 816K |
| 代理商： | MT45W2MV16BABB-856WT |
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2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
ADVANCE
09005aef80ec6f63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Burst CellularRAM_32.fm - Rev. A 2/18/04 EN
14
2004 Micron Technology, Inc. All Rights Reserved.
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is
reduced to the level necessary to perform the DRAM
refresh operation. Standby operation occurs when CE#
is HIGH.
The device will enter a reduced power state upon
completion of a READ or WRITE operation, or when
the address and control inputs remain static for an
extended period of time. This mode will continue until
a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) allows for
adequate refresh at different temperatures. This
CellularRAM device includes an on-chip temperature
sensor. When the sensor is enabled, it continually
adjusts the refresh rate according to the operating
temperature. The on-chip sensor is enabled by default.
Three fixed refresh rates are also available, corre-
sponding to temperature thresholds of +15°C, +45°C,
and +85°C. The setting selected must be for a tempera-
ture higher than the case temperature of the Cellular-
RAM device. If the case temperature is +35°C, the
system can minimize self-refresh current consump-
tion by selecting the +45°C setting. The +15°C setting
would result in inadequate refreshing and cause data
corruption.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation
to a portion of the total memory array. This feature
enables the device to reduce standby current by
refreshing only that part of the memory array required
by the host system. The refresh options are full array,
three-quarters array, one-half array, one-quarter array,
or none of the array. The mapping of these partitions
can start at either the beginning or the end of the
address map (see Table 9 on page 22). READ and
WRITE operations to address ranges receiving refresh
will not be affected. Data stored in addresses not
receiving refresh will become corrupted. When re-
enabling additional portions of the array, the new por-
tions are available immediately upon writing to the
RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all
refresh-related activity. This mode is used if the system
does not require the storage provided by the Cellular-
RAM device. Any stored data will become corrupted
when DPD is enabled. When refresh activity has been
re-enabled by rewriting the RCR, the CellularRAM
device will require 150s to perform an initialization
procedure before normal operations can resume. Dur-
ing this 150s period, the current consumption will be
higher than the specified standby levels, but consider-
ably lower than the active current specification.
DPD cannot be enabled or disabled by writing to
the RCR using the software access sequence; the RCR
should be accessed using CRE instead.
Configuration Registers
Two user-accessible configuration registers define
the device operation. The bus configuration register
(BCR) defines how the CellularRAM interacts with the
system memory bus and is nearly identical to its coun-
terpart on burst mode Flash devices. The refresh config-
uration register (RCR) is used to control how refresh is
performed on the DRAM array. These registers are
automatically loaded with default settings during
power-up, and can be updated any time the devices
are operating in a standby state.
Access Using CRE
The configuration registers are loaded using either a
synchronous or an asynchronous WRITE operation
when the configuration register enable (CRE) input is
LOW, a READ or WRITE operation will access the
memory array. The register values are placed on
address pins A[20:0]. In an asynchronous WRITE, the
values are are latched into the configuration register
on the rising edge of ADV#, CE#, or WE#, whichever
occurs first; LB# and UB# are “Don’t Care.” Access
using CRE is WRITE only. The BCR is accessed when
A[19] is HIGH; the RCR is accessed when A[19] is LOW.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT45W2MV16PFA-70 WT | 制造商:Micron Technology Inc 功能描述:2MX16 PSRAM PLASTIC WIRELESS TEMP FBGA 1.8V ASYNCH PSEUDO ST - Trays |
| MT45W2MW16BABB-706 L WT | 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:378 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-CBGA 供应商设备封装:48-CBGA（7x7） 包装:托盘 |
| MT45W2MW16BABB-706 L WT TR | 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Tape and Reel |
| MT45W2MW16BABB-706 WT | 制造商:Micron Technology Inc 功能描述:PSRAM Async 1 32M-Bit 2M x 16 70ns 54-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:PSRAM ASYNC 1 32MBIT 2MX16 70NS 54VFBGA - Trays 制造商:Micron Technology Inc 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA |
| MT45W2MW16BABB-706 WT TR | 功能描述:IC PSRAM 32MBIT 70NS 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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