- 您现在的位置：买卖IC网 > PDF目录385639 > MT46V4M32LG (Micron Technology, Inc.) I.MX31 LITE KIT PDF资料下载
参数资料
| 型号： | MT46V4M32LG |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | I.MX31 LITE KIT |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 14/66页 |
| 文件大小： | 1921K |
| 代理商： | MT46V4M32LG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页
14
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
Operations
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 4.
After a row is opened with an ACTIVE command, a
READ or WRITE command may be issued to that row,
subject to the
t
RCD specification.
t
RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a
t
RCD specifi-
cation of 15ns with a 166 MHz clock (6ns period) results
in 2.5 clocks rounded to 3. This is reflected in Figure 5,
which covers any case where 2 <
t
RCD (MIN)/
t
CK
≤
3.
(Figure 5 also shows the same case for
t
RCD; the same
procedure is used to convert other specification limits
from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
t
RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
Figure 5
Example: Meeting
t
RCD (
t
RRD) MIN When 2 <
t
RCD (
t
RRD) MIN/
t
CK
≤
3
Figure 4
Activating a Specific Row in
a Specific Bank
CS#
WE#
CAS#
RAS#
CKE
A0-A11
RA
RA = Row Address
BA = Bank Address
HIGH
BA0,1
BA
CK
CK#
COMMAND
BA0, BA1
ACT
ACT
NOP
tRRD
tRCD
CK
CK#
Bank
x
Bank
y
A0-A11
Row
Row
NOP
RD/WR
NOP
Bank
y
Col
NOP
T0
T1
T2
T3
T4
T5
T6
T7
DON T CARE
NOP
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
| MT48LC32M4A1 | ECONOLINE: RSZ/P - 1kVDC |
| MT48LC32M4A2 | SYNCHRONOUS DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V64M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
发布紧急采购，3分钟左右您将得到回复。