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参数资料
型号： MT46V4M32LG
厂商： Micron Technology, Inc.
英文描述： I.MX31 LITE KIT
中文描述： 双倍数据速率的DDR SDRAM内存
文件页数： 45/66页
文件大小： 1921K
代理商： MT46V4M32LG
45
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5,14-17,33,40; notes on pages 46-49) (0°C
≤
T
A
≤
+70°C; V
DD
Q = +2.5V ±0.125V, V
DD
= +2.5V ±0.125V)
AC CHARACTERISTICS
PARAMETER
SYMBOL
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
CL = 5
CL = 4
CL = 3
CL = 2
Auto precharge write recovery plus precharge time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time
Address and control input setup time
Address and control input pulse width
LOAD MODE REGISTER command cycle time
Power-Down Recovery Time
-33
-4
-5
MIN
-0.6
0.45
0.45
3.3
4
-
-
6
0.45
0.45
1.25
-0.6
0.4
0.4
MAX
+0.6
0.55
0.55
8
8
-
-
MIN
-0.7
0.45
0.45
-
4
5
-
6
0.45
0.45
1.25
-0.7
0.4
0.4
MAX
+0.7
0.55
0.55
-
8
8
-
MIN
-0.7
0.45
0.45
-
-
5
8
6
0.45
0.45
1.25
-0.7
0.4
0.4
MAX
+0.7
0.55
0.55
-
-
8
8
UNITS
ns
t
CK
t
CK
ns
ns
ns
ns
t
CK
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
t
CK
ns
NOTES
t
AC
t
CH
t
CL
t
CK(5)
t
CK(4)
t
CK(3)
t
CK(2)
t
DAL
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IH
t
IS
t
IPW
t
MRD
t
PDIX
30
30
26, 31
26, 31
31
+0.6
+0.7
+0.7
0.4
1.2
0.45
1.2
0.45
1.2
25, 26
0.8
0.25
0.25
t
CH,
t
CL
-0.5
-0.5
0.9
0.9
2
2
1
t
CK
+
t
IS
t
HP
-0.4ns
40
56
62
0.8
0.25
0.25
t
CH,
t
CL
-0.5
-0.5
0.9
0.9
2
2
1
t
CK
+
t
IS
t
HP
-0.4ns
40
56
62
0.8
0.25
0.25
t
CH,
t
CL
-0.5
-0.5
0.9
0.9
2
2
1
t
CK
+
t
IS
t
HP
-0.4ns
40
58
62
34
18
18
14
14
25, 26
34
25, 26
34
35
DQ-DQS hold, DQS to first DQ to go non-valid, per access
t
QH
ns
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
REFRESH to REFRESH command interval`
Average periodic refresh interval
ACTIVE to READ delay
ACTIVE to WRITE delay
PRECHARGE command period
DQS Read preamble
DQS Read postamble
ACTIVE bank
a
to ACTIVE bank
b
command
Terminating voltage delay to V
DD
DQS Write preamble
DQS Write preamble setup time
DQS Write postamble
Write recovery time
Internal WRITE to READ command delay
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Data valid output window
t
RAS
t
RC
t
RFC
t
REFC
t
REFI
t
RCDR
t
RCDW
t
RP
t
RPRE
t
RPST
t
RRD
t
VTD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
t
XSNR
t
XSRD
na
120,000
120,000
120,000
ns
ns
ns
μs
μs
ns
ns
ns
t
CK
t
CK
t
CK
ns
t
CK
ns
t
CK
t
CK
t
CK
ns
t
CK
ns
NA
7.8
NA
7.8
NA
7.8
23
23
16
10
16
0.9
0.4
3
16
10
16
0.9
0.4
3
20
10
20
0.9
0.4
2
1.1
0.6
1.1
0.6
1.1
0.6
42
0.25
0
0.4
3
1
66
200
t
QH-
t
DQSQ
0.25
0
0.4
3
1
66
200
t
QH-
t
DQSQ
0.25
0
0.4
2
1
66
200
t
QH-
t
DQSQ
20, 21
19
0.6
0.6
0.6
25
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