参数资料
型号: MT46V4M32LG
厂商: Micron Technology, Inc.
英文描述: I.MX31 LITE KIT
中文描述: 双倍数据速率的DDR SDRAM内存
文件页数: 63/66页
文件大小: 1921K
代理商: MT46V4M32LG
63
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
BANK WRITE – WITH AUTO PRECHARGE
TIMING PARAMETERS
-33
-4
-5
SYMBOL
t
CH
t
CL
t
CK (5)
t
CK (4)
t
CK (3)
t
DH
t
DS
t
DQSH
t
DQSL
t
DQSS
MIN
0.45
0.45
3.3
4
-
0.45
0.45
0.4
0.4
0.8
MAX
0.55
0.55
8
8
-
MIN
0.45
0.45
-
4
5
0.45
0.45
0.4
0.4
0.8
MAX
0.55
0.55
-
8
8
MIN
0.45
0.45
-
-
5
0.45
0.45
0.4
0.4
0.8
MAX
0.55
0.55
-
-
8
UNITS
t
CK
t
CK
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
1.2
1.2
1.2
-33
-4
-5
SYMBOL
t
DSS
t
DSH
t
IH
t
IS
t
RAS
t
RCDW
t
RP
t
WPRE
t
WPRES
t
WPST
t
WR
MIN
0.25
0.25
0.9
0.9
40
10
16
0.25
0
0.4
3
MAX
MIN
0.25
0.25
0.9
0.9
40
10
16
0.25
0
0.4
3
MAX
MIN
0.25
0.25
0.9
0.9
40
10
20
0.25
0
0.4
2
MAX
UNITS
t
CK
t
CK
ns
ns
ns
ns
ns
t
CK
ns
t
CK
t
CK
120,000
120,000
120,000
0.6
0.6
0.6
CK
CK#
CKE
A8
BA0, BA1
t
CK
t
CH
tCL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
t
IS
t
IH
RA
t
RCD
t
RAS
t
DSH
6
t
RP
t
WR
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T4n
A0-A7
A9-A11
NOTE:
1. DI
n
= data-out from column
n
; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6.tDSH is applicable during tDQSS(MIN)
and is referenced from CK T4 or T5.
7.tDSS is applicable during tDQSS (MAX)
and is referenced from CK T5 or T6.
NOP5
NOP5
COMMAND
4
3
ACT
RA
RA
Col
n
WRITE2
NOP5
Bank
x
NOP5
Bank
x
NOP5
NOP5
NOP5
t
DQSL
t
DQSH
t
WPST
t
DSS
7
t
DSH
6
t
DSS
7
DQ
1
DQS
DM
DI
b
t
DS
t
DH
t
DQSS (NOM)
DON’T CARE
TRANSITIONING DATA
t
WPRES
t
WPRE
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