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| 型号： | MT46V8M8 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8 x 4 banks DDR SDRAM(2 M x 8 x 4组，双数据速率同步动态RAM) |
| 中文描述： | 2梅格× 8 × 4银行DDR SDRAM内存（2米× 8 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 10/69页 |
| 文件大小： | 2369K |
| 代理商： | MT46V8M8 |
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10
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
Figure 1
Mode Register Definition
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a
block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A
i
when the burst length is set to two, by
A2-A
i
when the burst length is set to four and by A3-A
i
when the burst length is set to eight (where A
i
is the
most significant column address bit for a given con-
Table 1
Burst Definition
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
A0
0
1
2
0-1
1-0
0-1
1-0
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
A2 A1 A0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
NOTE:
1. For a burst length of two, A1-A
i
select the two-
data-element block; A0 selects the first access
within the block.
2. For a burst length of four, A2-A
i
select the four-
data-element block; A0-A1 select the first access
within the block.
3. For a burst length of eight, A3-A
i
select the eight-
data-element block; A0-A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency BT
0*
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
Valid
Valid
-
M6-M0
0
1
-
M8
0
0
-
M7
Operating Mode
A10
A11
BA1
BA0
10
11
12
13
* M13 and M12 (BA0 and BA1)
must be
“
0, 0
”
to select the
base mode register (vs. the
extended mode register).
0
0
-
M9
0
0
-
M10
0
0
-
M11
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
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