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参数资料
| 型号： | MT46V8M8 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8 x 4 banks DDR SDRAM(2 M x 8 x 4组，双数据速率同步动态RAM) |
| 中文描述： | 2梅格× 8 × 4银行DDR SDRAM内存（2米× 8 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 11/69页 |
| 文件大小： | 2369K |
| 代理商： | MT46V8M8 |
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11
64Mb: x4, x8, x16 DDR SDRAM
64Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 10/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb: x4, x8, x16
DDR SDRAM
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON
’
T CARE
TRANSITIONING DATA
Table 2
CAS Latency
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 2.
If a READ command is registered at clock edge
n
,
and the latency is
m
clocks, the data will be available
nominally coincident with clock edge
n + m
. Table 2
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 2
CAS Latency
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A11
each set to zero, and bits A0-A6 set to the desired values.
A DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9-A11 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. When a LOAD MODE REGISTER command is
issued to reset the DLL, it should always be followed by
a LOAD MODE REGISTER command to select normal
operating mode.
All other combinations of values for A7-A11 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because un-
known operation or incompatibility with future ver-
sions may result.
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
CL = 2
83 ≤
f
≤
133
83 ≤
f
≤
100
83 ≤
f
≤
100
CL = 2.5
83 ≤
f
≤
143
83 ≤
f
≤
133
83 ≤
f
≤
125
-7
-75
-8
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