参数资料
型号: MT48LC4M32LFB5-10ES:G
元件分类: DRAM
英文描述: 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90
封装: 8 X 13 MM, LEAD FREE, VFBGA-90
文件页数: 4/69页
文件大小: 6213K
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
12
2001 Micron Technology, Inc. All rights reserved.
Functional Description
In general, the 128Mb SDRAMs (2 Meg x16 x 4 banks
and 1 Meg x 32 x 4 banks) are quad-bank DRAMs that
operate at 3.3V or 2.5V and include a synchronous
interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the x16’s 33,554,432-
bit banks is organized as 4,096 rows by 512 columns by
16 bits. Each of the x32’s 33,554,432-bit banks is orga-
nized as 4,096 rows by 256 columns by 32bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0-A11 select the row).
The address bits (x16: A0-A8; x32: A0-A7) registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation
covering
device
initialization,
register
definition, command descriptions and device opera-
tion.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to Vdd and VddQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100s delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100s period and continuing at least through the
end of this period, Command Inhibit or NOP com-
mands should be applied.
Once the 100s delay has been satisfied with at least
one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All banks must then be precharged, thereby placing
the device in the all banks idle state.
Once in the idle state, two AUTO refresh cycles must
be performed. After the AUTO refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.
Register Definition
Mode Register
In order to achieve low power consumption, there
are two mode registers in the Mobile component,
Mode Register and Extended Mode Register. For this
section, Mode Register is referred to. Extended Mode
register is discussed on 15. The mode register is used to
define the specific mode of operation of the SDRAM.
This definition includes the selection of a burst length,
a burst type, a CAS latency, an operating mode and a
write burst mode, as shown in Figure 7. The mode reg-
ister is programmed via the LOAD MODE REGISTER
command and will retain the stored information until
it is programmed again or the device loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specify the Write Burst
mode (single or programmed burst length), M10, and
M11 are reserved and must be set to zero. To address
the mode register M12 and M13 must be set to zero.
The mode register must be loaded when all banks
are idle, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in Figure 8 on page 14. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types,
and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with
the BURST TERMINATE command to generate arbi-
trary burst lengths. If a full page burst is not termi-
nated at the end of the page it could wrap to column
zero and continue.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A8 (x16) or A1-A7 (x32) when the burst
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