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参数资料
| 型号： | MT48LC4M32LFB5-10ES:G |
| 元件分类： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封装： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件页数： | 42/69页 |
| 文件大小： | 6213K |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
47
2001 Micron Technology, Inc. All rights reserved.
Notes
1. All voltages are referenced to Vss
2. This parameter is sampled. VDD, VDDQ = +3.3V; TA
= 25°C; pin under test biased at 1.4V., f = 1 MHz,
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full operational temperature range is
ensured (TA
= Commercial, IT or XT).
6. An initial pause of 100s is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously.
VSS and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a mono-
tonic manner.
9. Outputs measured at 1.5V (for LC devices) or at
1.25V (V devices) with equivalent load:
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests use established values for
VIL and VIH, with timing referenced to VIH/2
crossover point. If the input transition time is
longer than 1ns, then the timing is referenced at
VIL(MAX) and VIH(MIN) and no longer at the VIH/2
crossover point. Established tester values follow:
VIL = 0V, VIH = 3.0V for LC devices, and VIH = 2.3V
for V devices.
12. Other input signals are allowed to transition no
more than once every two clocks and are other-
wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
14. Timing actually specified by tCKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 125MHz for -8 and tCK = 100MHz
for -10.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width
≤ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL under-
shoot: VIL (MIN) = -2V for a pulse width
≤ 3ns and
can not be greater than one third of the cycle rate.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing tWR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins at 5.4ns for -8 after the first
clock delay, after the last WRITE is executed.
25. Manual Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. Parameter guaranteed by design.
28. PC100 specifies a maximum of 4pF.
29. PC100 specifies a maximum of 5pF.
30. PC100 specifies a maximum of 6.5pF.
31. For -75M, CL=3 and tCK = 7.5ns; For -8, CL = 3 and
tCK = 8ns; for -10, CL = 3 and tCK =10ns.
32. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a
fail value.
33. Specified with I/Os in steady state condition.
Q
30pF
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