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参数资料
| 型号： | NAND04GW4B3BN1F |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 256M X 16 FLASH 3V PROM, 35 ns, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件页数： | 19/59页 |
| 文件大小： | 998K |
| 代理商： | NAND04GW4B3BN1F |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
26/59
Cache Program
The Cache Program operation is used to improve
the programming throughput by programming
data using the Cache Register. The Cache Pro-
gram operation can only be used within one block.
The Cache Register allows new data to be input
while the previous data that was transferred to the
Page Buffer is programmed into the memory ar-
ray.
Each Cache Program operation consists of five
steps (refer to Figure 16.):
1.
First of all the program setup command is
issued (one bus cycle to issue the program
setup command then four bus write cycles to
input the address), the data is then input (up to
2112 Bytes/ 1056 Words) and loaded into the
Cache Register.
2.
One bus cycle is required to issue the confirm
command to start the P/E/R Controller.
3.
The P/E/R Controller then transfers the data to
the Page Buffer. During this the device is busy
for a time of tWHBH2.
4.
Once the data is loaded into the Page Buffer
the P/E/R Controller programs the data into
the memory array. As soon as the Cache
Registers are empty (after tWHBH2) a new
Cache program command can be issued,
while the internal programming is still
executing.
Once the program operation has started the Sta-
tus Register can be read using the Read Status
Register command. During Cache Program oper-
ations SR5 can be read to find out whether the in-
ternal programming is ongoing (SR5 = ‘0’) or has
completed (SR5 = ‘1’) while SR6 indicates wheth-
er the Cache Register is ready to accept new data.
If any errors have been detected on the previous
page (Page N-1), the Cache Program Error Bit SR1
will be set to ‘1', while if the error has been detect-
ed on Page N the Error Bit SR0 will be set to '1’.
When the next page (Page N) of data is input with
the Cache Program command, tWHBH2 is affected
by the pending internal programming. The data will
only be transferred from the Cache Register to the
Page Buffer when the pending program cycle is
finished and the Page Buffer is available.
If the system monitors the progress of the opera-
tion using only the Ready/Busy signal, the last
page of data must be programmed with the Page
Program confirm command (10h).
If the Cache Program confirm command (15h) is
used instead, Status Register bit SR5 must be
polled to find out if the last programming is finished
before starting any other operations.
Figure 16. Cache Program Operation
Note: 1. Up to 64 pages can be programmed in one Cache Program operation.
2. tCACHEPG is the program time for the last page + the program time for the (last 1)
th page
(Program command cycle time + Last
page data loading time).
I/O
RB
Address
Inputs
ai08672
80h
Page
Program
Code
Read Status
Register
Busy
Data
Inputs
15h
Cache
Program
Code
80h
Page
Program
Code
15h
Cache Program
Confirm Code
Busy
Last Page
tBLBH5
(Cache Busy time)
tBLBH5
tCACHEPG
SR0
70h
80h
10h
Page
Program
Confirm Code
Busy
First Page
Second Page
(can be repeated up to 63 times)
Address
Inputs
Data
Inputs
Address
Inputs
Data
Inputs
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相关代理商/技术参数 |
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|---|---|
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| NAND08GAH0JZC5E | 功能描述:IC FLASH 8GBIT 52MHZ 153LFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.173"，4.40mm 宽） 供应商设备封装:8-MFP 包装:带卷 (TR) |
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