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参数资料
型号： NCN6001DTBEVB
厂商： ON Semiconductor
文件页数： 27/36页
文件大小： 0K
描述： EVAL BOARD FOR NCN6001DTB
设计资源： NCN6001DTBEVB Gerber Files
NCN6001 Demo Brd Schematic
NCN6001DBEVB BOM
标准包装： 1
主要目的： 接口，智能卡
嵌入式： 是，MCU，8 位
已用 IC / 零件： NCN6001
主要属性： 与 ISO 7816-3，EMV，GIE-CB 兼容
次要属性： 符合 GSM 规定
已供物品： 板
其它名称： NCN6001DTBEVBOS
NCN6001
http://onsemi.com
33
Table of Contents
COMPACT SMART CARD INTERFACE IC
1
.......
MAXIMUM RATINGS
6
.........................
DIGITAL PARAMETERS SECTION
8
..............
POWER SUPPLY SECTION
9
....................
SMART CARD INTERFACE SECTION
10
..........
PROGRAMMING
11
.............................
STARTUP DEFAULT CONDITIONS
14
............
CARD DETECTION
14
..........................
CRD_VCC OPERATION
14
......................
POWERUP SEQUENCE
14
......................
POWER DOWN SEQUENCE
16
..................
DATA I/O LEVEL SHIFTER
17
...................
GENERAL PURPOSE CRD_C4 and CRD_C8
18
.....
INTERRUPT
19
................................
SPI PORT
20
...................................
DC/DC OPERATION
22
.........................
SMART CARD CLOCK DIVIDER
26
..............
INPUT SHITTY TRIGGERS
28
...................
SECURITY FEATURES
28
.......................
ESD PROTECTION
28
..........................
PRINTED CIRCUIT BOARD LAY OUT
28
.........
TEST BOARD SCHEMATIC DIAGRAM
29
.........
ABBREVIATIONS
34
...........................
DIMENSIONS
35
...............................
Figures Index
Figure 1. Pin Connections
2
.......................
Figure 2. Typical Application
3
....................
Figure 3. Block Diagram
3
........................
Figure 4. Typical Startup CRD_VCC Sequence
14
.....
Figure 5. CRD_VCC Typical Rise and Fall Time
15
....
Figure 6. Startup Sequence with ATR
15
.............
Figure 7. Typical Power Down Sequence
16
..........
Figure 8. Basic I/O Internal Circuit
17
...............
Figure 9. Typical I/O Rise and Fall Time
17
..........
Figure 10. Typical CRD_C4 Output Drive and Logic
Control
18
.....................................
Figure 11. Basic Interrupt Function
19
...............
Figure 12. Basic SPI Timings and Protocol
20
.........
Figure 13. Chip Address Decoding Protocol and MISO
Sequence
20
...................................
Figure 14. Basic Multi Command SPI Bytes
21
........
Figure 15. Programming Sequence, Chip Address = $03
21
............................................
Figure 16. MISO Read Out Sequences
22
............
Figure 17. Basic DC/DC Converter
22
...............
Figure 18. Theoretical DC/DC Operating Waveforms
23
............................................
Figure 19. Typical CRD_VCC Ripple Voltage
24
......
Figure 20. CRD_VCC Efficiency as a Function of the
Input Supply Voltage
24
..........................
Figure 21. CRD_VCC Efficiency as a Function of the
Input Supply Voltage
24
..........................
Figure 22. Typical Inductor Current
25
..............
Figure 23. Output Current Limits
25
................
Figure 24. Output Current Limit as a Function of the
Temperature
25
.................................
Figure 25. Typical Clock Divider Synchronization
26
...
Figure 26. Basic Clock Divider and Level Shifter
26
....
Figure 27. Force CRD_CLK to Low
27
..............
Figure 28. Force CRD_CLK to Active Mode
27
.......
Figure 29. CRD_CLK Programming
27
..............
Figure 30. CRD_CLK Operating Low Speed (Top Trace),
Full Speed (Bottom Trace)
27
......................
Figure 31. Typical Schmitt Trigger Characteristic
28
....
Figure 32. NCN6001 Engineering Test Board Schematic
Diagram
29
....................................
Figure 33. NCN6001 Demo Board Printed Circuit Board
Layout
30
.....................................
Figure 34. Typical Multiple Parallel Interfaces
32
......
Tables Index
DIGITAL PARAMETERS
8
......................
POWER SUPPLY.
9
.............................
SMART CARD INTERFACE.
10
..................
Table 1. WRT_REG Bits Definitions
11
...............
Table 2. WRT_REG Bits Definitions and Functions
12
..
Table 3. MOSI and MISO Bits Identifications and
Functions
13
...................................
Table 4. Startup Default Conditions
14
...............
Table 5. CRD_VCC Output Voltage Range
14
.........
Table 6. I/O Pullup Resistor True Table
17
...........
Table 7. Interrupt Reset Logic
19
...................
Table 8. Interrupt Reset Logic Operation
19
..........
Table 9. Ceramic/Electrolytic Capacitors Comparison
24
............................................
Table 10. Output Clock Rise and Fall Time Selection
27
............................................
Table 11. Demo Board Bill of Material
31
............
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