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| 型号： | NCP1027P065G |
| 厂商： | ON Semiconductor |
| 文件页数： | 23/30页 |
| 文件大小： | 0K |
| 描述： | IC SWIT PWM PROG CM OVP HV 8DIP |
| 标准包装： | 1,000 |
| 输出隔离： | 隔离 |
| 频率范围： | 58.5kHz ~ 71.5kHz |
| 输入电压： | 7.9 V ~ 10 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 25W |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm），7 引线 |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 其它名称： | NCP1027P065GOS |
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NCP1027
The principle consists in selecting the RR resistor,
connected from pin 2 to ground, to impose a current I RR in
the transistor collector.
Np:Ns = 1:N = 1:0.052 transformer turn ratio
Lp = 3.8 mH primary inductance
We can calculate the off slope, the one actually needed
to evaluate S a , by reflecting the output voltage over the
primary inductance. The slope is projected over a complete
switching period. Here, we use a 65 kHz part.
Soff + out
V ) Vf
NLp
TSW +
6
0.052
15u
3.8m
+ 455 mA 15 m s
(eq. 10)
Due to the internal sense arrangement, this current slope
will become a voltage slope having a value of:
S off + 455m
0.375 + 170 mV 15 m s (eq. 11)
If we chose 50% of this downslope, then the final
compensation ramp will present a slope of:
Sa + 170m + 85 mV 15 m s
We then have:
2
(eq. 12)
2.75k + 89 k W
Figure 41. Maximum Peak Current Setpoint
Variations versus Ramp Compensation
RR +
Vp2.75 k
Sa@TSW
+ 2.75
85m
(eq. 13)
In the above calculations, the internal ESD resistor has
The equation to get the right compensation level is the
following:
purposely been omitted to avoid bringing in another
variable. In case no ramp compensation is required, pin 2
RR +
Vp2.75 k
Sa@TSW
(eq. 9)
must be tied to V CC , the adjacent pin.
Soft-Start
where Vp, the total voltage swing, equals 2.75 V.
Application example:
Suppose we have the following flyback specifications:
Vout = 5.0 V output voltage
Vf = 1.0 V secondary diode forward drop
@ Iout nominal
The NCP1027 features a 1.0 ms soft-start, which
reduces the power-on stress, but also contributes to lower
the output overshoot. Figure 42 shows a typical operating
waveform. The NCP1027 features a novel patented
structure which offers a better soft-start ramp, almost
ignoring the startup pedestal inherent to traditional
current-mode supplies.
Figure 42. 1.0 ms Soft-Start Sequence
http://onsemi.com
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