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| 型号： | NCP1027P065G |
| 厂商： | ON Semiconductor |
| 文件页数： | 25/30页 |
| 文件大小： | 0K |
| 描述： | IC SWIT PWM PROG CM OVP HV 8DIP |
| 标准包装： | 1,000 |
| 输出隔离： | 隔离 |
| 频率范围： | 58.5kHz ~ 71.5kHz |
| 输入电压： | 7.9 V ~ 10 V |
| 输出电压： | 700V |
| 功率（瓦特）： | 25W |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm），7 引线 |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 其它名称： | NCP1027P065GOS |
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NCP1027
5.0 V/3.0 A Universal Mains Power Supply
Due to its low R DS(on) , the NCP1027 can be used in
universal mains SMPS up to 15 W of continuous power,
provided that the chip power dissipation is well under
control. That is to say that average power calculations and
measurements have been carried and correlated. The
design of an SMPS around a monolithic device does not
differ from that of a standard circuit using a controller and
a MOSFET. However, one needs to be aware of certain
characteristics specific of monolithic devices. Let us
follow the steps:
V in min = 120 Vdc
V in max = 375 Vdc
V out = 5.0 V
V out = 15 W
Operating mode is CCM
h = 0.8
1. The lateral MOSFET body- diode shall never be
forward biased, either during startup (because of a
large leakage inductance) or in normal operation
as shown by Figure 45. This condition sets the
maximum voltage that can be reflected during t off .
350
250
150
50.0
> 0 !!
-
50.0
1.004M
1.011M
1.018M
1.025M
1.032M
+ 110 + 18.3 or
Vin
5 ) 1
Vout ) Vf
d max +
+
+ 0.49
NVout ) Vin, min
(eq. 16)
1 ) NV
Figure 45. The reflected voltage shall always be greater
than the minimum input voltage to avoid the forward
biasing of the MOSFET body-diode.
As a result, the Flyback voltage which is reflected on the
drain at the switch opening cannot be larger than the input
voltage. When selecting components, you thus must adopt
a turn ratio which adheres to the following equation:
N(Vout ) Vf) t Vin, min t Vin min (eq. 14) . In our case,
since we operate from a 120 V DC rail while delivering
5.0 V, we can select a reflected voltage of 110 V
DC maximum: 120-110 > 0. Therefore, the turn ratio
Np:Ns must be smaller than
Np : Ns t 19 . We will see later on how it affects the
calculation.
2. Lateral MOSFETs have a poorly doped
body-diode which naturally limits their ability to
sustain the avalanche. A traditional RCD
clamping network shall thus be installed to
protect the MOSFET. In some low power
Figure 46. Primary Inductance Current
Evolution in CCM
turn ratio, V out the output voltage, V f the
secondary diode forward drop and finally, I peak
the maximum peak current. Worse case occurs
when the SMPS is very close to regulation, e.g.
the V out target is almost reached and I peak is still
pushed to the maximum. For this design, we have
selected our maximum voltage around 650 V (at
V in = 375 Vdc). This voltage is given by the RCD
clamp installed from the drain to the bulk
voltage. We will see how to calculate it later on.
3. Calculate the maximum operating duty-cycle for
this flyback converter operated in CCM:
NVout 1
Vin,min
out
4. To obtain the primary inductance, we have the
choice between two equations:
) Ipeak
(eq. 15) , where L f is the leakage
L + , where K +
and
applications, a simple capacitor can also be used
since Vdrain max + Vin ) N (Vout ) Vf)
Lf
Ctot
inductance, C tot the total capacitance at the drain
node (which is increased by the capacitor you
will wire between drain and source), N the Np:Ns
?
(Vind)2 D IL
(eq. 17)
fSWKPin I1
defines the amount of ripple we want in CCM
(see Figure 46).
Small K: deep CCM, implying a large primary
inductance, a low bandwidth and a large leakage
inductance.
http://onsemi.com
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